1. Field of the Invention
The present invention relates to a semiconductor device and, in particular, to a pad layout in a semiconductor device.
2. Background Art
Semiconductor devices, such as semiconductor integrated circuits, have incorporated increasingly complicated circuit blocks along with increases in their functionality and scale. Moreover, a greater number of pads have been provided as a connection interface with an external device in such a semiconductor device. Therefore, to reduce the size of such a semiconductor device, it is necessary not only to form a finer circuit block but also to create device design including a pad layout and wiring from the pads to the circuit block.
For example, Japanese Patent Application Laid-Open No. 2004-179184 discloses a semiconductor integrated circuit including: an internal cell region formed in a central part of a substrate; a plurality of input and output cells formed around the internal cell region and arranged in a plurality of rows; and a plurality of pads formed in a peripheral portion of the substrate, in which input and output cells constituting a relatively-inner input and output cell row are connected to the pads via wiring formed above input and output cells constituting a relatively-outer input and output cell row.
Japanese Patent Application Laid-Open No. 2012-235048 discloses a semiconductor device including: a plurality of first buffer cells provided in a row along one side of a substrate; a plurality of second buffer cells provided in a row along the arrangement direction of the plurality of first buffer cells at positions closer to a center of the substrate than the plurality of first buffer cells; a plurality of first pads provided in a row above the plurality of first buffer cells; and a plurality of second pads provided in a row at positions closer to the center of the substrate than the plurality of first buffer cells, in which the plurality of second pads include: a plurality of third pads each individually connected to any one of the plurality of first buffer cells; and a plurality of fourth pads each individually connected to any one of the plurality of second buffer cells.